Integrated circuits (ICs) generally include various modules combined to perform various functions. For example, a digital signal processor (DSP) may include processor and memory modules. The modules are tested for defects, ensuring the operability of the IC. To test the modules, special test circuits, referred to as “Built-In Self Test” (BIST) circuits are incorporated into the IC.
An area of interest is the testing of the on-chip memory module. The memory module is tested by a memory BIST to determine whether the memory module is defective or not. In some cases, if the number of defective memory cells is relatively low, the IC may still be salvaged using redundant cells. However, most conventional memory BISTs only identify whether any defects exist in memory module, not the location or number of defects in the memory module. Without knowing the defective addresses, they can not be repaired with redundant cells. Furthermore, the testing of memory requires extensive amount of time, particularly with larger memories.
As evidenced from the above discussion, it is desirable to provide a memory BIST capable of testing memory faster and identifying defective locations.